The apparatus of the present invention generally relates to data processing systems and more particularly to data processing operations provided over a common input/output bus.
In a system having a plurality of devices coupled over a common bus an orderly system must be provided by which bidirectional transfer of information may be provided between such devices. This problem becomes more complicated when such devices include for example one or more data processors, one or more memory units and various types of peripheral devices, such as magnetic tape storage devices, disk storage devices, card reading equipment, and the like.
Various methods and apparatus are known in the prior art for interconnecting such a system. Such prior art systems range from those having common data bus paths to those which have special paths between various devices. Such systems also may include a capability for either synchronous or asynchronous operation in combination with the bus type. Some of such systems, independent of the manner in which such devices are connected or operate, require the central processor's control of any such data transfer on the bus even though for example the transfer may be between devices other than the central processor. In addition, such systems normally include various parity checking apparatus, priority schemes and interrupt structures. One such structural scheme is shown in U.S. Pat. No. 3,866,181. Another is shown in U.S. Pat. No. 3,676,860. A data processing system utilizing a common bus is shown in U.S. Pat. No. 3,815,099. The manner in which addressing is provided in such systems as well as the manner in which for example any one of the devices may control the data transfer is dependent upon the implementation of the system, i.e., whether there is a common bus, whether the operation thereof is synchronous or asynchronous, etc. The system's response and throughput capability is greatly dependent on these various structures.
A particular structural scheme is shown in U.S. Pat. Nos. 3,993,981, 3,995,258, 3,997,896, 4,000,485, 4,001,790 and 4,030,075 which describe an asynchronously operated common bus. The present invention is an improvement thereon in which the system throughput capabilities are improved by allowing a device on the common data bus to request that another device on the common data bus provide the requesting device with multiple words of information. The present invention provides for the multiple word request to be made in a single bus cycle and the requested information to be provided in a series of responding bus cycles. This method increases system throughput by reducing the number of bus request cycles that would otherwise be required. Other data processing systems, although allowing for multiple words to be requested, require that the data bus be as wide as the number of words to be returned in a single response cycle. In the present invention, the common data bus need only be one word wide and multiple response cycles are provided to deliver one word of requested information during each response cycle.
It is accordingly a primary objective of the present invention to provide an improved data processing system having a plurality of devices, including the central processor, connected to a common bus in a manner that permits a device during one bus cycle to request multiple words of information be delivered by another device during a series of response bus cycles.